Computer systems and other electronic systems typically use buses for interconnecting integrated circuit components so that the components may communicate with one another. The buses frequently connect a master, such as a microprocessor or controller, to slaves, such as memories and bus transceivers. Generally, a master may send data to and receive data from one or more slaves. A slave may send data to and receive data from a master, but not another slave.
Each master and slave coupled to a prior bus typically includes output driver circuitry for driving signals onto the bus. Some prior bus systems have output drivers that use transistor-transistor logic (“TTL”) circuitry. Other prior bus systems have output drivers that include emitter-coupled logic (“ECL”) circuitry. Other output drivers use complementary metal-oxide-semiconductor (“CMOS”) circuitry or N-channel metal-oxide-semiconductor (“NMOS”) circuitry.
While many prior buses were driven by voltage level signals, it has become advantageous to provide buses that are driven by a current mode output driver. A benefit associated with a current mode driver is a reduction of peak switching current. In particular, the current mode driver draws a known current regardless of load and operating conditions. A further benefit is that the current mode driver typically suppresses noise coupled form power and ground supplies.
A known current mode driver is shown in U.S. Pat. No. 5,254,883 (the “'883 patent”), which is assigned to the assignee of the present invention and incorporated herein by reference. The '883 patent discusses an apparatus and method for setting and maintaining the operating current of a current mode driver. The driver in the '883 patent includes an output transistor array, output logic circuitry coupled to the transistor array and a current controller coupled to the output logic circuitry.
For one embodiment, the current controller in the '883 patent is a resistor reference current controller. The current controller receives two input voltages, VTERM and VREF, the latter of which is applied to an input of a comparator. VTERM is coupled by a resistor to a node, which is in turn coupled to a second input of the comparator. The voltage at the node is controlled by a transistor array, which is in turn controlled in accordance with an output of the comparator.
When the transistor array is placed in the “off” state, i.e. there is no current flowing through the transistors of the array to ground, the voltage at the node is equal to VTERM. In addition, by using the output of the comparator to adjustably activate the transistor array, the '883 patent shows that the voltage at the node may be driven to be approximately equal to the reference voltage, VREF.
Knowing the value of VREF and VTERM, the current mode driver of the '883 patent therefore provides a binary signaling scheme utilizing a symmetrical voltage swing about VREF. Specifically, in a first current state (the “off” state), the current mode driver is not sinking current and the signal line (or bus line) is at a voltage, VO=VTERM, representing a logical “0.” In a second current state (the “on” state), the current mode driver is sinking current to drive the voltage on the signal line (or bus line) to be:VO=VTERM−2(VTERM−VREF)
The second state therefore representing a logical “1.”
While the binary signal levels are commonly used, the use of multi-level signals is a known technique for increasing the data rate of a digital signaling system. Such multi-level signaling is sometimes known as multiple pulse amplitude modulation or multi-PAM, and has been implemented with radio or other long-distance wireless signaling systems. Other long-distance uses for multi-PAM signaling include computer or telecommunication systems that employ Gigabit Ethernet over optical fiber and over copper wires, which use three and five signal levels, respectively.
Additionally, multi-PAM signaling may be used for communication between devices in close proximity or belonging to the same system, such as those connected to the same integrated circuit (“IC”) or printed circuit board (“PCB”). In such systems, the characteristics of transmission lines, such as buses or transmission lines, over which the signals travel are tightly controlled, so that the increase in the data rate may be increased by increasing the transmit frequency. However, at higher frequencies, receiving devices may have a reduced ability to distinguish binary signals. Further, for cases in which attenuation of a signal exists between transmission and reception, different amounts of signal loss may occur depending upon the magnitude of transition between logic states. To compensate for the attenuation of the received signal, different equalization signals may be added to the main signal when driving different transitions in order to add predetermined high-frequency components to the transition signals that raise the slope of the edge of the transition. However, a difficulty with this approach for a typical multi-PAM system is that the voltage can only be pulled down from the VTERM, unless negative current could flow through current sources. To allow overdriving a transition with the equalization signals, the highest logic state may, therefore, be reduced below VTERM. This may cause the respective reference voltages to be no longer centered on the shifted data eyes.
Further, in a system that has numerous closely spaced signal lines, such as a bus for a computer device or a similar device, crosstalk may exist between nearby lines. As is known in the art, crosstalk is a disturbance caused by the electric or magnetic fields of one telecommunication signal and impairs signals on adjacent signal lines. Crosstalk characteristics on a bus may be based upon how many lines are between a crosstalk creator and a signal line being affected by crosstalk. One method for crosstalk cancellation has been described in the co-pending U.S. Patent Application entitled “Low Latency Equalization in Multi-Level, Multi-Line Communication Systems,” identified above. Similarly to the equalization mechanism, the crosstalk cancellation provides high frequency component signal and, thus, the highest logic state of the system is typically reduced below VTERM, causing reference voltage levels to be no longer centered on the shifted data eyes.
Thus, it is still desirable to develop a method and system for reference voltage generation that would track the logic state shifts due to equalization or crosstalk